All-digital multi-standard transmitters architecture using delta-sigma modulators

ABSTRACT

The present disclosure is concerned with a digital transmitter using Delta-Sigma modulators (DMSs) that uses an up-sampler and modulator block that follows the DSMs to generate the RF equivalent of the baseband signal to be transmitted. The up-sampler and modulator block is simple to implement and contains only one or a few multiplexers implemented in high speed logic technology.

FIELD

The present invention generally relates to transmitter architectures.More specifically, the present invention is concerned with a digitaltransmitter architecture using low-frequency Delta-Sigma Modulators(DSMs) cascaded with binary up-sampler and modulator block working athigher frequency.

BACKGROUND

The new generation of communication standards uses complex modulationtechniques in order to gain more spectrum efficiency. These modulationtypes generate signals with high varying envelopes that generally imposestringent constraints on the linearity versus power efficiency trade-offof power amplifiers. Traditional transmitter architectures includelinear power amplifiers (class A or class AB) operated in back-off,which results in poor efficiency performances.

On the other hand, the proliferation and diversity of communicationstandards motivates the research to design a multi-standard transceiverthat can be used for different communication standards. One expensiveapproach consists in dedicating one transmitter for each standard andswitch between them depending of the input signal type or standard.

The digital transceiver, generally consisting in implementing a greatportion of a transceiver in the digital domain, is another solution.Indeed, the digital transceiver is easily configured to be compliantwith different standards. One approach in the design of such a digitaltransmitter is the use of Delta-sigma modulation (DSM) technique. Thistechnique is used to transform the envelope and phase modulated basebandsignal in one digital bit stream representing the signal. This techniquealso shapes the quantization noise outside of the useful bandwidth.

BRIEF DESCRIPTION OF THE DRAWINGS

In the appended drawings:

FIG. 1A is a general block diagram of a first digital transmitter basedon delta-sigma modulation (DSM);

FIG. 1B is a general block diagram of a second digital transmitter basedon delta-sigma modulation (DSM);

FIG. 2 is a block diagram illustrating the architecture of a delta-sigmatransmitter based on two DSMs according to a first illustrativeembodiment of the present invention;

FIG. 3A is a block diagram of a first illustrative embodiment of theup-sampler and modulator block for the delta-sigma transmitterillustrated in FIG. 2;

FIG. 3B is a block diagram of a second illustrative embodiment of theup-sampler and modulator block for the delta-sigma transmitterillustrated in FIG. 2;

FIG. 4 is a block diagram illustrating the architecture of a delta-sigmatransmitter based on one DSM according to a second illustrativeembodiment of the present invention;

FIG. 5 is a block diagram of an illustrative embodiment of theup-sampler and modulator block for the delta-sigma transmitterillustrated in FIG. 4;

FIG. 6 is a block diagram illustrating an example of a low pass thirdorder delta-sigma modulator that can be used in the embodimentsillustrated in FIGS. 2 and 4;

FIGS. 7A to 7C show some typical measurement results testing theperformance of the illustrated embodiments of the present invention; and

FIG. 8 is a block diagram illustrating a hardware design allowingobtaining an EDGE signal having a bandwidth of about 200 kHz andcentered on an RF frequency equal to 950 MHz, and a WiMAX signal havinga bandwidth equal to 1.25 MHz and centered on an RF frequency equal to2.5 GHz.

DETAILED DESCRIPTION

In accordance with an illustrative embodiment of the present invention,there is provided a digital transmitter producing a binary stream outputsignal at a desired RF carrier frequency from an envelope or an envelopeand phase varying input signal, the digital transmitter comprising:

at least one delta-sigma modulator so configured as to receive andconvert the input signal into a complementary binary stream pair;

an up-sampler and modulator so configured as to receive and transformthe complementary binary stream signal pair into the binary streamoutput signal at the desired RF carrier frequency;

wherein the delta-sigma modulator operates at a clock frequencyindependent from the RF carrier frequency.

In accordance with another aspect of the present invention, there isprovided a digital transmitter assembly producing an amplified binarystream output signal from an envelope or an envelope and phase modulatedinput signal, the digital transmitter assembly comprising:

-   -   a digital transmitter including:        -   at least one delta-sigma modulator so configured as to            receive and convert the input signal to a complementary            binary stream pair;        -   an up-sampler and modulator so configured as to receive and            transform the complementary binary stream signal pair to the            desired RF carrier frequency;    -   a band pass filter receiving the binary stream signal from the        digital transmitter; the band pass filter being so configured as        to reject the quantization noise present in the binary stream        signal; and    -   a power amplifier so connected to the band pass filter as to        receive the filtered binary stream signal from the band pass        filter; the power amplifier being so configured as to linearly        amplify the filtered binary stream signal to yield the amplified        binary stream output signal.

According to another aspect of the present invention, there is provideda digital transmitter assembly producing an amplified binary streamoutput signal from an envelope or an envelope and phase modulated inputsignal, the digital transmitter assembly comprising:

-   -   a digital transmitter including:        -   at least one delta-sigma modulator so configured as to            receive and convert the input signal to a complementary            binary stream pair;        -   an up-sampler and modulator so configured as to receive and            transform the complementary binary stream signal pair to the            desired RF carrier frequency;    -   a power amplifier receiving the binary stream signal from the        digital transmitter; the power amplifier being so configured as        to linearly amplify the binary stream signal; and    -   a band pass filter so connected to the power amplifier as to        receive the amplified binary stream signal from the power        amplifier; the band pass filter being so configured as to reject        the quantization noise present in the amplified binary stream        signal to yield an amplified binary stream output signal. The        present description refers to other documents listed at the end        of the present disclosure. These documents are hereby        incorporated by reference in their entirety.

The use of the word “a” or “an” when used in conjunction with the term“comprising” in the claims and/or the specification may mean “one”, butit is also consistent with the meaning of “one or more”, “at least one”,and “one or more than one”. Similarly, the word “another” may mean atleast a second or more.

As used in this specification and claim(s), the words “comprising” (andany form of comprising, such as “comprise” and “comprises”), “having”(and any form of having, such as “have” and “has”), “including” (and anyform of including, such as “include” and “includes”) or “containing”(and any form of containing, such as “contain” and “contains”), areinclusive or open-ended and do not exclude additional, unrecitedelements or process steps.

Other objects, advantages and features of the present invention willbecome more apparent upon reading of the following non-restrictivedescription of illustrative embodiments thereof, given by way of exampleonly with reference to the accompanying drawings.

The present invention uses Delta-Sigma modulators (DSMs). As isgenerally known to those skilled in the art, these modulators generate abinary flow stream representing the baseband or the low-IF signal to betransmitted. Generally stated, the present invention proposes theimplementation of an up-sampler and modulator block that follows theDSMs to generate the RF equivalent of the baseband signal to betransmitted. The RF signal is also a higher frequency bit stream signal.As will be apparent from the following disclosure, the up-sampler andmodulator block is simple to implement and contains only one or a fewmultiplexers implemented in high speed logic technology. Only themultiplexer works at the RF frequency.

Consequently, the proposed technology reduces the constraints on thespeed of the DSMs allowing a possible increase in their order andconsequently an improvement in the signal quality.

Generally stated, the present invention concerns the implementation of adigital transmitter for wireless or wired communication networks suchas, for example, terrestrial wireless communication, satellitecommunication, data networks and audio and video wireless and wiredbroadcasting. The digital transmitter has many advantages compared tothe traditional analog transmitter. As non-limiting examples, thedigital transmitter results in better signal quality, it is easy to beconfigured to comply with different standards without duplicating thehardware, it may also increase the transmitter over all power efficiencyby reducing the energy consumption of the power amplifier and the analogcomponents.

FIGS. 1A and 1B each show a general block diagram of a digitaltransmitter. In the first scenario of FIG. 1A, the band-pass filter(BPF) 3 is applied at the output of the power amplifier (PA) 2. In thesecond scenario of FIG. 1B, the BPF 3 it is applied to the signal beforeits amplification by the PA 2.

In both cases, the input signal to the digital transmitter 1 is anenvelope or an envelope and phase modulated signal. The input signal canbe analog or digital, real or complex envelope, and baseband ormodulated around an IF frequency. The digital transmitter 1 transformsthe envelope varying signal into a high speed binary stream signal 4representing the signal up-converted to the RF frequencies. Due to thesignal transformation from envelope varying to binary stream,quantization noise is present in the signal spectrum adjacent to signalband. In addition, signal 4 contains harmonics with power level lessthan the signal power level around the fundamental.

In the first scenario of FIG. 1A, the power amplifier 2 receives thebinary stream signal 4 as an input. In this case, an efficient PA suchas, for example, a switching mode PA or a highly nonlinear PA can beused without altering the signal quality. The amplified signal 5 at theoutput of the PA 2 is also a binary stream having the same sequence asthe binary stream signal 4 but having a higher power. The band-passfilter 3 selects the signal around the fundamental or one of theharmonics and rejects the quantization noise present in the amplifiedsignal 5. The resulting output signal 6 is an envelope varying signal,which represents a linearly amplified version of the input signal.

In the second scenario of FIG. 1B, the binary stream 4 is filteredbefore amplification. Like the input signal, the filtered binary streamsignal 8 is envelope varying. The digital transmitter 1 and BPF 3operate as a traditional transmitter but with high signal qualitygeneration. The PA 2 amplifies the filtered binary stream signal 8. Inthis case, the PA 2 could be any linear power amplifier structure. Thismay include, but is not necessary limited to, class A, class AB,Push-pull, LINC and Doherty with or without a linearization techniquesuch as digital and analog pre-distortion, feedback, feed forward,envelope tracking, envelope elimination and restoration, etc.

Turning now to FIG. 2, the details of the architecture of the digitaltransmitter 1 according to a first illustrative embodiment will bedescribed.

FIG. 2 schematically illustrates, in block diagram form, a digitaltransmitter 1 to be used when the input signal is a complex envelopecomposed of separate I and Q signal components.

The digital transmitter 1 includes an input 10, first and second DSMs 11and 12, an up-sampler and modulator 13 and a clock generator 30.

It is to be noted that the clock generator 30 could be separate from theother elements of the digital transmitter 1.

Each of the I and Q signal components may be baseband or translatedaround an IF frequency. They may be analog or digital. The first andsecond DSMs 11 and 12 transform the envelope varying signals I and Qinto complementary binary stream pairs 21, 22 and 23, 24. DSMs 11 and 12operate at low clock frequencies compared to the RF carrier frequency.The frequency of operation of the DSMs 11 and 12 is independent from thecarrier frequency and depends only on the signal bandwidth andspecification. The architecture of DSMs 11 and 12 can be the same forall types of signals and will be discussed hereinbelow with reference toFIG. 6.

The complementary binary stream pair 21, 22 is the complementary binarystream pair corresponding to I component of the input signal and thecomplementary binary stream pair 23, 24 is the complementary binarystream pair corresponding to Q component of the input signal. Theup-sampler and modulator block 13 processes these two pairs of signalsto provide the RF pulse-shaped binary stream signal 4 as the output ofthe digital transmitter 1. The up-sampler and modulator 13 operates athigher frequency than the DSMs 11 and 12. Indeed, contrary to the DSMs11 and 12, the frequency of operation of the up-sampler and modulator 13depends mainly on the carrier frequency of the signal. The frequency ofoperation of the up-sampler and modulator 13 is related to the carrierfrequency according to the following formulae:

$f_{33} = {2\left( {\frac{f_{c}}{N} - f_{b}} \right)}$ and$f_{34} = {4\left( {\frac{f_{c}}{N} - f_{b}} \right)}$where f₃₃ is the frequency of clock 33; f₃₄ is the frequency of clock34; f_(c) is the desired RF carrier frequency; f_(b) is the IF carrierfrequency of the signals I and Q at the input of the DSMs 11 and 12(f_(b)=0 if I and Q are baseband signals; and N is the number of theharmonic of the signal 4 considered as useful signal.

FIGS. 3A and 3B show two illustrative embodiments of the up-sampler andmodulator block 13 of the transmitter 1 of FIG. 2. The up-sampler andmodulator block 13 can be implemented using one (FIG. 3B) or many (FIG.3A) multiplexers. These multiplexers alternate at their frequency ofoperation in the given order the signals 21, 23, 22, and 24. Thisoperation modulates the I and Q signals around a carrier defined by theclock frequency of the multiplexers.

FIG. 3A illustrates the case of three 2:1 multiplexers 201, 202 and 203,where the clock 33 frequency is the multiplexing frequency for themultiplexers 201 and 202 and has a frequency equal to about double thedifference between the desired carrier frequency of the output signaland the input signal carrier frequency as defined hereinabove. The clock34 frequency is the multiplexing frequency for the multiplexer 203 andhas a frequency equal to about double the frequency of the clock 33 asdefined hereinabove.

FIG. 3B illustrates the case of one 4:1 multiplexer 204 where the clock34 frequency is the multiplexing frequency and has a value equal toabout four times the difference between the desired carrier frequency ofthe output signal and the input signal carrier frequency as definedhereinabove.

In both embodiments of the up-sampler and modulator block 13 of FIGS. 3Aand 3B, the main function is the same and consists in up-sampling allthe signals at a high frequency. This up-sampling frequency is adjustedaccording to the carrier frequency of the signal. After up-sampling,signal pairs 21, 22 and 23, 24 are modulated around a carrier frequency.A choice of an up-sampling speed equal to about double the differencebetween the desired carrier frequency of the output signal and the inputsignal carrier frequency (in the case of the first embodiment suggestionin FIG. 3A) and about four time the carrier frequency (in the case ofthe second embodiment suggestion in FIG. 3B) allows the quadraturemodulation of the I and Q transformed component signals (thecomplementary pairs 21, 22 and 23, 24) to maintain a binary streamresult for the modulated binary stream signal 4. This is due to the factthat the multiplication of a symbol I with a cosine wave functionsampled at about four times the carrier frequency results in arepetition of the following sequence I 0 Ī 0. And the multiplication ofa symbol Q with a sine wave function sampled at about four times thecarrier frequency results in a repetition of the following sequence 0 Q0 Q. Consequently, the sum of both sequences is equal to I Q Ī Q, whichcan be implemented as suggested in FIGS. 3A and 3B.

The illustrative embodiments of FIGS. 3A and 3B generally avoid anyphase shift of the local oscillator signal, usually used in traditionalarchitectures. Consequently, in addition to lowering the quantizationnoise floor compared to a traditional architecture, the proposedtechnology has the potential to reduce the gain and phase imbalance inthe transmitter resulting in better signal quality.

Turning now to FIG. 4 of the appended drawings, the details of thearchitecture of a digital transmitter 100 according to a secondillustrative embodiment will be described.

FIG. 4 generally corresponds to the case of one branch signal such as areal envelope signal in baseband or modulated around RF frequency or acomplex envelope signal modulated around an IF frequency. In this case,only one DSM 111 converts the input envelope varying signal to acomplementary binary stream pair 121, 122. Then the up-sampler andmodulator block 113 transforms this complementary binary stream signalpair to the desired RF frequency. In this configuration, the DSM 111runs at a slow clock frequency independent from the carrier frequency.Only the up-sampler and modulator block 113 runs at about twice thecarrier frequency.

FIG. 5 shows an illustrative embodiment of the up-sampler and modulatorblock 113 illustrated in FIG. 4. As can be seen from this figure, thesignals at the input of the modulator block 113 are the outputcomplementary binary stream pair 121, 122 from the DSM 111. Theup-sampler and modulator 113, in this case, is a 2:1 multiplexer 301.The multiplexing frequency of 301 is the frequency of clock 133, whichis related to the desired RF carrier frequency as follows:

$f_{133} = {2\left( {\frac{f_{c}}{N} - f_{b^{\prime}}} \right)}$where f₁₃₃ is the frequency of clock 133; f_(c) is the desired RFcarrier frequency; f_(b′) is the IF carrier frequency of the inputsignal of the DSM 111 (f_(b′)=0 if this signal is a baseband signal);and N is the number of the harmonic of the signal 4 considered as usefulsignal.

In the illustrative embodiment of FIG. 5, the main function of the block113 is generally to up-sample the signal at higher frequency. Thisup-sampling frequency is adjusted according to the desired carrierfrequency and the input signal carrier frequency (IF frequency for IFsignals and zero for baseband signals). After up-sampling, the signal ismodulated around a carrier frequency. The choice of an up-samplingfrequency around twice the carrier frequency generates a binary streamat the output of block 113 representing the signal around the carrierfrequency. This is true since a multiplication of the signal S with sinewave sampled at twice the carrier frequency corresponds to thealternation of the sequence S S, which corresponds to the alternationbetween both branches of the complementary pair of the signal at thementioned frequency. The illustrative embodiment of FIG. 5 can beconfigured easily compared to traditional transmitters' embodiments.Besides, the illustrative embodiment of FIG. 5 introduces less leakagethat is usually present in traditional transmitters.

FIG. 6 shows a typical block diagram of a third order delta-sigmamodulator that may be used in the illustrative embodiments shown inFIGS. 2 and 4. The structure contains three integrators 151, 152 and 153with feedback loops 191 and 192. The outputs from each integrator arescaled using gain blocks 161, 162 and 163 and then summed by summator143 to generate the output 185. This output 185 is then quantized intoone complementary binary stream pair output by the level detector 171.The output signal 180, 181 of the delta-sigma modulator is then acomplementary binary stream pair having the quantization noise shapedoutside the useful bandwidth. The delta-sigma modulation theory is wellknow to those of ordinary skill in the art and, therefore, will not befurther described in the present specification.

It will be apparent to one skilled in the art that other types ofdelta-sigma modulators, such as, for example band pass or a differenttopology of low pass, can be used in the illustrative embodimentspresented in FIGS. 2 and 4, instead of the DSM illustrated in FIG. 6.

FIGS. 7A to 7C presents some typical measurement results of the proposedillustrative digital transmitter embodiments. The standards used in thisillustration are not restrictive. The technology can be applied to anykind of signal and any type of application that comprises but notnecessarily limited to wireless data networking standards (such as WLAN,WiMAN), wireless data communication standards (such as UMTS, GSM, EDGE),satellite applications (such as GPS, Satellite radio, DVB, satellitecommunication applications) and Custom signal waveforms for specificpurpose applications (such as military applications). The signalmodulation can be BPSK, QPSK, QAM, PSK, FSK, GMSK. These signals can becombined with any channel division multiplex techniques and/or anymultiple access technique such as FDMA, TDMA, CDMA, OFDM, WCDMA.

FIG. 7A presents an example of the signal at the output of the DSM 111(the pair 121, 122) of FIG. 4. The signal has a bandwidth of 30 KHz andis centered around 80 MHz IF frequency. The DSM used in this test is afifth order delta-sigma modulator (not shown).

FIGS. 7B and 7C show the results of binary stream signal 4 for an EDGEsignal and a WiMAX signals respectively. EDGE and WiMAX are twostandards that can be used with the proposed technology. The proposedtechnology can be used with any standard for wireless and satellitecommunication application. It can be used for wired transmissionstandards us well. There is no limitations that prevent the presenttechnology to be used with a well established standard or signal typesfor specific purposes such as signals used in military applications. Thefollowing is a list of different standards and applications where thetechnology can be applied. However, this list is not restrictive:

-   -   Wireless data network standards: IEEE802.11a, IEEE802.11b,        IEEE802.11g, HiperLAN I, HiperLAN II, WiMAX;    -   Wireless Communication standards: UMTS, GSM, GPRS, EDGE;    -   Satellite Communications;    -   Satellite broadcasting applications: GPS, satellite radio, DVB;        and    -   Custom signal waveforms for specific purpose applications such        as military applications. The signal modulation can be BPSK,        QPSK, QAM, PSK, FSK, GMSK. These signals can be combined with        any channel division multiplex techniques and/or any multiple        access technique such as FDMA, TDMA, CDMA, OFDM, WCDMA.

The EDGE signal of FIG. 7B has a bandwidth of about 200 kHz and iscentered on an RF frequency equal to about 950 MHz. The WiMAX signal ofFIG. 7C has a bandwidth equal to 1.25 MHz and is centered on an RFfrequency equal to 2.5 GHz. Both results are obtained using the samehardware as shown in FIG. 8.

FIG. 8 is an example of implementation of the architecture in FIG. 2combined with FIG. 3A. The third order DS modulators 11 and 12 isimplemented in the FPGA EP1S80 evaluation board from Altera Inc. TheNB7L86M evaluation board from On semiconductor Inc. is used to implementthe multiplexers 201, 202, and 203. The switching mode class F PA isdesigned from the RT233 transistor from RFHIC Inc. The only change tothe transmitter of FIG. 8 for the Edge and the WiMAX signals is thefrequency of the clock signals 31, 33, 34. The frequencies of the clocks33 and 34 are defined hereinabove, and the frequency of the clock 31 isnot related to the carrier frequency. It will be understood that thefrequency of this clock 31 determines the quality of the signal: thehigher is the frequency, the better is the signal quality.

In the illustrative case of the measurement results given in FIG. 7, theclock signals of the hardware set-up of FIG. 8 are set as follows: forthe EDGE signal, the clocks 31, 33 and 34 are set to 160 MHz, 1900 MHzand 3800 MHz, respectively, while for the WiMAX signal, the clocks 31,33 and 34 are set to 200 MHz, 5000 MHz and 10000 MHz respectively. TheDSM order and type may also change to give better trade-off betweensignal quality and hardware complexity.

The illustrative embodiments described hereinabove are easily configuredfor a given standard and are suitable for multi-standard applicationssince they offers a low cost, low complexity and better performancesolution. The modulation and signal types, the bandwidth and the carrierfrequency presented in these measurements are only examples to give anidea about the performances of the technology. Of course, the capabilityof the illustrative embodiments is not limited to such signal andmodulation types and bandwidths.

It will be apparent to one skilled in the art that the illustrativeembodiments of the digital transmitters described hereinabove may bearranged and constructed in discrete, semi-discrete, surface mount,multi-chip, or monolithic technology for utilization in one of themobile station and base station for wireless communication and in oneuser terminal and server application for wired or wireless networks.

The illustrative embodiments described herein also make possible thegeneration of signals around RF frequency in the range of few Giga Hertz(GHz). As mentioned hereinabove, changing the frequency is easy toachieve by only changing the clock frequency and generally does notrequire a considerable change in the transmitter architecture.

As is easily understood by one skilled in the art, the proposedillustrative embodiments are easy to implement and may require only onesignal clock. When this is the case, there is no need to synchronize twodifferent clock signals and/or to adjust the gain and phase of thesignal at different stages of the implemented structure. This reducesthe cost of the implementation in terms of resources and energyconsumption and ensures good signal quality. Consequently, the risks ofalgorithm divergence or bad adjustment performances are minimized.

For example, the digital transmitter 1 of FIG. 2 uses either:

-   -   one clock signal if the topology of FIG. 3B is used: the clock        frequency 34 is generally equal or close to four times the        carrier frequency;    -   two (2) clock signals if the topology of FIG. 3A is used: the        first clock frequency 33 is generally equal or close to twice        the carrier frequency and the second clock frequency 34 is        generally equal or close to four times the carrier frequency.

The digital transmitter 100 of FIG. 4 uses one clock signal 133 equal orclose to twice the carrier frequency.

It is to be understood that the invention is not limited in itsapplication to the details of construction and parts illustrated in theaccompanying drawings and described hereinabove. The invention iscapable of other embodiments and of being practiced in various ways. Itis also to be understood that the phraseology or terminology used hereinis for the purpose of description and not limitation. Hence, althoughthe present invention has been described hereinabove by way ofillustrative embodiments thereof, it can be modified, without departingfrom the spirit, scope and nature of the subject invention as defined inthe appended claims.

REFERENCES

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What is claimed is:
 1. A digital transmitter producing a binary streamoutput signal at a desired RF carrier frequency from an amplitude oramplitude and phase varying baseband modulated or IF modulated inputsignal, the digital transmitter comprising: at least one delta-sigmamodulator operating at a first clock frequency independent from thedesired RF carrier frequency and so configured as to receive and convertthe amplitude or amplitude and phase varying baseband modulated or IFmodulated input signal into a complementary binary stream pair having afirst data rate equal to the first clock frequency and having a carrierfrequency equal to zero or to an intermediate frequency; an up-samplerand modulator so configured as to receive and multiplex, at a secondclock frequency independent from the first clock frequency, thecomplementary binary stream pair to transform the complementary binarystream pair into the binary stream output signal having a second datarate greater than the first data rate, greater than the desired RFcarrier frequency, and calculated as a function of the desired RFcarrier frequency; wherein the digital transmitter is an all-digitaltransmitter that maintains all signals in binary stream format betweenthe at least one delta-sigma modulator and an output of the up-samplerand modulator.
 2. The digital transmitter recited in claim 1, whereinthe at least one delta-sigma modulator includes one delta-sigmamodulator.
 3. The digital transmitter recited in claim 2, furthercomprising a clock generator so configured as to generate a clock signalto be supplied to the up-sampler and modulator.
 4. The digitaltransmitter recited in claim 3, wherein the frequency of the clocksignal supplied to the up-sampler and modulator is about at least twicethe desired RF carrier frequency.
 5. The digital transmitter recited inclaim 3, wherein the clock generator so configured as to generate aclock signal to be supplied to the delta-sigma modulator.
 6. The digitaltransmitter recited in claim 2, wherein the up-sampler and modulatorincludes a multiplexer.
 7. The digital transmitter recited in claim 6,wherein the multiplexer is a 2:1 multiplexer that is so configured as toreceive the complementary binary stream pair as inputs; the output ofthe 2:1 multiplexer defining the binary stream output signal.
 8. Thedigital transmitter recited in claim 1, wherein: the input signal is acomplex envelope composed of separate I and Q signal components; and theat least one delta-sigma modulator includes a first and seconddelta-sigma modulators; the first delta-sigma modulator receiving the Isignal component and the second delta-sigma modulator receiving the Qsignal component; the first and second delta-sigma modulatorsrespectively generating first and second complementary binary streampairs.
 9. The digital transmitter recited in claim 8, further comprisinga clock generator so configured as to generate a clock signal at thesecond clock frequency to be supplied to the up-sampler and modulator.10. The digital transmitter recited in claim 9, wherein the clockgenerator is so configured as to generate a clock signal at the firstclock frequency to be supplied to the delta-sigma modulator.
 11. Thedigital transmitter recited in claim 9, wherein the frequency of theclock signal at the second clock frequency supplied to the up-samplerand modulator is about four times the desired RF carrier frequency. 12.The digital transmitter recited in claim 11, wherein the up-sampler andmodulator includes a 4:1 multiplexer that is so configured as to receivethe first and second complementary binary stream pair as inputs; theoutput of the 4:1 multiplexer being the binary stream output signal. 13.The digital transmitter recited in claim 11, wherein the clock generatoris further configured to generate another clock signal having afrequency about twice the desired RF carrier.
 14. The digitaltransmitter recited in claim 13, wherein the up-sampler and modulatorincludes: a first 2:1 multiplexer that is so configured as to receive afirst complementary binary stream pair as inputs; the first 2:1multiplexer receiving the clock signal having the frequency about twicethe desired RF carrier; a second 2:1 multiplexer that is so configuredas to receive a second complementary binary stream pair as inputs; thesecond 2:1 multiplexer receiving the clock signal having the frequencyabout twice the desired RF carrier; a third 2:1 multiplexer that is soconfigured as to receive the outputs of the first and second 2:1multiplexers as inputs; the third 2:1 multiplexer receiving the clocksignal having the frequency about four times the desired RF carrierfrequency; the output of the 2:1 multiplexer defining the binary streamoutput signal.
 15. The digital transmitter recited in claim 1,comprising a low pass delta-sigma modulator.
 16. A digital transmitterassembly producing an amplified binary stream output signal from anamplitude or amplitude and phase, baseband or IF, modulated inputsignal, the digital transmitter assembly comprising: a digitaltransmitter including: at least one delta-sigma modulator operating at afirst clock frequency independent from the desired RF carrier frequencyand so configured as to receive and convert the amplitude or amplitudeand phase, baseband or IF, modulated input signal to a complementarybinary stream pair having a first data rate equal to the first clockfrequency and having a carrier frequency equal to zero or to anintermediate frequency; an up-sampler and modulator so configured as toreceive and multiplex, at a second clock frequency independent from thefirst clock frequency, the complementary binary stream pair to transformthe complementary binary stream pair to a binary stream output signalhaving a second data rate greater than the first data rate, greater thanthe desired RF carrier frequency, and calculated as a function of thedesired RF carrier frequency; a band pass filter receiving the binarystream output signal from the digital transmitter; the band pass filterbeing so configured as to reject the quantization noise present in thebinary stream output signal; and a power amplifier so connected to theband pass filter as to receive the filtered binary stream output signalfrom the band pass filter; the power amplifier being so configured as tolinearly amplify the filtered binary stream signal to yield theamplified binary stream output signal; wherein the digital transmitteris an all-digital transmitter that maintains all signals in binarystream format between the at least one delta-sigma modulator and anoutput of the up-sampler and modulator.
 17. The digital transmitterassembly recited in claim 16, comprising a low pass delta-sigmamodulator.
 18. A digital transmitter assembly producing an amplifiedfiltered binary stream output signal from an amplitude or amplitude andphase, baseband or IF, modulated input signal, the digital transmitterassembly comprising: a digital transmitter including: at least onedelta-sigma modulator operating at a first clock frequency independentfrom the desired RF carrier frequency and so configured as to receiveand convert the amplitude or amplitude and phase, baseband or IF,modulated input signal to a complementary binary stream pair having afirst data rate equal to the first clock frequency and having a carrierfrequency equal to zero or to an intermediate frequency; an up-samplerand modulator so configured as to receive and multiplex, at a secondclock frequency independent from the first clock frequency, thecomplementary binary stream pair to transform the complementary binarystream pair to a binary stream output signal having a second data rategreater than the first data rate, greater than the desired RF carrierfrequency, and calculated as a function of the desired RF carrierfrequency; a power amplifier receiving the binary stream output signalfrom the digital transmitter; the power amplifier being so configured asto linearly amplify the binary stream output signal; and a band passfilter so connected to the power amplifier as to receive the amplifiedbinary stream output signal from the power amplifier; the band passfilter being so configured as to reject the quantization noise presentin the amplified binary stream signal to yield the amplified filteredbinary stream output signal; wherein the digital transmitter is anall-digital transmitter that maintains all signals in binary streamformat between the at least one delta-sigma modulator and an output ofthe up-sampler and modulator.
 19. The digital transmitter assemblyrecited in claim 18, comprising a low pass delta-sigma modulator.